View TLE6208-3G_8178226.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

p-dso-14-9 enhanced power triple-half-bridge tle 6208-3 g data sheet 1 2001-05-10 1 overview 1.1 features ? three half-bridges optimized for dc motor management applications delivers up to 0.6 a continuous, 1.2 a peak current r ds on ; typ. 0.8 ? , @ 25 c per switch output: short circuit protected and diagnosis overtemperature-protection with hysteresis and diagnosis standard spi-interface/daisy chain capable very low current consumption in stand-by (inhibit) mode (typ. 10 a for power and 2 a for logic supply, @ 25 c) over- and undervoltage-lockout cmos/ttl compatible inputs with hysteresis no crossover current internal clamp diodes enhanced power p-dso-package programming compatibility to the tle 5208-6 g functional description the tle 6208-3 g is a fully protected tri ple- h alf- b ridge- d river designed specifically for automotive and industrial motion control applications. the part is based on the siemens power technology spt ? which allows bipolar and cmos control circuitry in accordance with dmos power devices existing on the same monolithic circuitry. in motion control up to 2 actuators (dc-motors) can be connected to the 3 halfbridge- outputs (cascade configuration). operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard spi-interface. the possibility to control the outputs via software from a central logic, allows limiting the power dissipation. so the standard p-dso-14-package meets the application requirements and saves pcb-board-space and cost. furthermore the build-in features like over- and undervoltage-lockout, over-temperature-protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications. type ordering code package tle 6208-3 g q67006-a9334 p-dso-14-9
tle 6208-3 g data sheet 2 2001-05-10 1.2 pin configuration (top view) figure 1 leadframe 8 9 10 11 12 13 14 7 6 5 4 2 3 1 chip gnd do inh out 2 out 1 gnd gnd clk di out 3 v cc s v p-dso-14-9 aep02438 gnd csn
tle 6208-3 g data sheet 3 2001-05-10 1.3 pin definitions and functions pin no. symbol function 1gnd ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab; to reduce thermal resistance place cooling areas on pcb close to these pins. 2out3 halfbridge-output 3; internally contected to highside-switch 3 and lowside-switch 3. the hs-switch is a power-mos open drain with internal reverse diode; the ls-switch is a power-mos open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. 3 v s power supply; needs a blocking capacitor as close as possible to gnd value: 22 f electrolytic in parallel to 220 nf ceramic. 5di serial data input; receives serial data from the control device; serial data transmitted to di is an 16bit control word with the least significant bit (lsb) being transferred first: the input has an active pull down and requires cmos logic level inputs; di will accept data on the falling edge of clk-signal; see table input data protocol . 4csn chip-select-not input; csn is an active low input; serial communication is enabled by pulling the csn terminal low; csn input should only be transitioned when clk is low; csn has an internal active pull up and requires cmos logic level inputs. 6clk serial clock input; clocks the shiftregister; clk has an internal active pull down and requires cmos logic level inputs. 7, 8, 14 gnd ground; see pin 1. 9do serial-data-output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on chip-select-not (csn); see table diagnosis data protocol . 10 inh inhibit input; has an internal pull down; device is switched in standby condition by pulling the inh terminal low. 11 v cc logic supply voltage; needs a blocking capacitor as close as possible to gnd; value: 10 f electrolytic in parallel to 220 nf ceramic. 12 out2 halfbridge-output 2; see pin 2. 13 out1 halfbridge-output 1; see pin 2.
tle 6208-3 g data sheet 4 2001-05-10 1.4 functional block diagram figure 2 block diagram bias inhibit charge pump detect fault- spi 16 bit logic and latch ov uv tsd >1 11 3 1,7,8,14 2 12 13 10 4 5 6 9 gnd out 2 out 1 out 3 do clk di csn inh v cc s v aeb02439 drv1 drv2 drv3
tle 6208-3 g data sheet 5 2001-05-10 1.5 circuit description figure 2 shows a block schematic diagram of the module. there are 3 halfbridge drivers on the right-hand side. an hs driver and an ls driver are combined to form a halfbridge driver in each case. the drivers communicate via the internal data bus with the logic and the other control and monitoring functions: undervoltage (uv), overvoltage (ov), overtemperature (tsd), charge pump and fault detect. two connection interfaces are provided for supply to the module: all power drivers are connected to the supply voltage v s . these are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. the logic is supplied by the v cc voltage, typ. with 5 v. the v cc voltage uses an internally generated power-on reset (por) to initialize the module at power-on. the advantage of this system is that information stored in the logic remains intact in the event of short- term failures in the supply voltage v s . the system can therefore continue to operate following v s undervoltage, without having to be reprogrammed. the ? undervoltage ? information is stored, and can be read out via the interface. the same logically applies for overvoltage. ? interference spikes ? on v s are therefore effectively suppressed. the situation is different in the case of undervoltage on the v cc connection pin. if this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). the module is initialized by v cc following restart (power-on reset = por). the 16-bit wide programming word or control word (see table input data protocol ) is read in via the di data input, and this is synchronized with the clock input clk. the status word appears synchronously at the do data output (see table diagnosis data protocol ). it is also possible to connect two tle 6208-3 g in a daisy chain configuration. the do data output of one device is connected with the di data input of the second device. in this configuration these two devices are controlled with a single csn chip select and using a 32-bit wide control word. the transmission cycle begins when the chip is selected with the csn input (h to l). if the csn input changes from l to h then the word which has been read in becomes the control word. the do output switches to tristate status at this point, thereby releasing the do bus circuit for other uses. the inh inhibit input can be used to cut off the complete module. this reduces the current consumption to just a few a, and results in the loss of any data stored. the output levels are switched to tristate status. the module is reinitialized with the internally generated por (power-on reset) at restart. this feature allows the use of this module in battery-operated applications (vehicle body control applications).
tle 6208-3 g data sheet 6 2001-05-10 every driver block from drv 1 to 3 contains a low-side driver and a high-side driver. both drivers are connected internally to form a half-bridge at the output. this reduction of output pins was necessary to meet the small p-dso-14 package. when commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. a special, integrated ? timer ? for power on/off times ensures that there is no crossover current. input data protocol diagnosis data protocol bit bit 15 ovlo on/off 15 power supply fail 14 not used 14 underload 13 overcurrent sd on/off 13 overload 12 not used 12 not used 11 not used 11 not used 10 not used 10 not used 9 not used 9 not used 8 not used 8 not used 7 not used 7 not used 6 hs-switch 3 6 status hs-switch 3 5 ls-switch 3 5 status ls-switch 3 4 hs-switch 2 4 status hs-switch 2 3 ls-switch 2 3 status ls-switch 2 2 hs-switch 1 2 status hs-switch 1 1 ls-switch 1 1 status ls-switch 1 0 status register reset 0 temp. prewarning h=on l=off h=on l=off
tle 6208-3 g data sheet 7 2001-05-10 fault result table fault diag.-bit result overcurrent (load) 13 only the failed output is switched off. function can be deactivated by bit no. 13. short circuit to gnd (high-side-switch) 13 only the failed output is switched off. function can be deactivated by bit no. 13. short circuit to v s (low-side-switch) 13 only the failed output is switched off. function can be deactivated by bit no. 13. temperature warning 0 reaction of control device needed. temperature shut down (sd) ? all outputs off. temperature warning is set before. underload/openload 14 reaction of control device needed. undervoltage lockout (uvlo) 15 all outputs off. overvoltage lockout (ovlo) 15 all outputs off. function can be deactivated by bit no. 15. h = failure; l = no failure.
tle 6208-3 g data sheet 8 2001-05-10 note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 electrical characteristics 2.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. supply voltage v s ? 0.3 40 v ? supply voltage v s ? 1 ? v t < 0.5 s; i s > ? 2 a logic supply voltage v cc ? 0.3 5.5 v 0 v < v s < 40 v logic input voltages (di, clk, csn, inh) v i ? 0.3 5.5 v 0 v < v s < 40 v 0 v < v cc < 5.5 v logic output voltage (do) v do ? 0.3 5.5 v 0 v < v s < 40 v 0 v < v cc < 5.5 v output voltage (out 1-3) v out ? 0.3 40 v 0 v < v s < 40 v output current (cont.) i out1-3 ?? a internal limited output current (peak) i out1-3 ?? a internal limited note: current limits are mentioned in the overcurrent section of electrical charateristics junction temperature t j ? 40 150 c ? storage temperature t stg ? 50 150 c ? esd voltage, human body model, according to: mil std 883d, ansi eos\esd s5.1 jedec jesd22-a114 v esd-hbm ?? 4kv all pins v esd-hbm- out ?? 8kv only pins 2, 12 and 13 (outputs) esd voltage, mashine model, according to: ansi eos\esd s5.2 jedec jesd22-a115 v esd-mm ?? 300v all pins
tle 6208-3 g data sheet 9 2001-05-10 note: in the operating range, the functions given in the circuit description are fulfilled. 2.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv off 40 v after v s rising above v uv on supply voltage slew rate d v s / d t ? 10 v/ s ? logic supply voltage v cc 4.75 5.50 v ? supply voltage increasing v s ? 0.3 v uv on v outputs in tristate supply voltage decreasing v s ? 0.3 v uv off v outputs in tristate logic input voltage (di, clk, csn, inh) v i ? 0.3 v cc v ? spi clock frequency f clk ? 1mhz ? junction temperature t j ? 40 150 c ? thermal resistances junction pin r thj-pin ? 30 k/w measured to pin 1, 7, 8, 14 junction ambient r thja ? 65 k/w ?
tle 6208-3 g data sheet 10 2001-05-10 2.3 electrical characteristics 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. current consumption quiescent current i s ? 820 a inh = low; v s = 13.2 v t j = 25 c quiescent current i s ?? 30 a inh = low; v s = 13.2 v; logic-supply current i cc ? 210 a inh = low logic-supply current i cc ? 1 2 ma spi not active supply current i s ? 25ma ? over- and under-voltage lockout uv-switch-on voltage v uv on ? 6.5 7 v v s increasing uv-switch-off voltage v uv off 5.6 6.1 6.6 v v s decreasing uv-on/off-hysteresis v uv hy ? 0.4 ? v v uv on ? v uv off ov-switch-off voltage v ov off 34 37 40 v v s increasing ov-switch-on voltage v ov on 30 33 36 v v s decreasing ov-on/off-hysteresis v ov hy ? 4 ? v v ov off ? v ov on
tle 6208-3 g data sheet 11 2001-05-10 outputs out1-3 static drain-source-on resistance source (high-side) i out = ? 0.5 a r ds on h ? 0.8 0.95 ? 8v < v s < 40 v t j = 25 c ? 1.6 ? 8v < v s < 40 v 1 ? ? v soff < v s 8v t j = 25 c ? 2 ? v soff < v s 8v sink (low-side) i out = 0.5 a r ds on l ? 0.75 0.9 ? 8v < v s < 40 v t j = 25 c ? 1.5 ? 8v < v s < 40 v 1 ? ? v soff < v s 8v t j = 25 c ? 2 ? v soff < v s 8v leakage current source-output-stage 1 to 3 i qlh ? 5 ? 1 ? a v out1-3 = 0 v sink-output-stage 1 to 3 i qll ? 150 300 a v out1-3 = v s overcurrent source shutdown threshold i sdu ? 2 ? 1.3 ? 1a ? sink shutdown threshold i sdl 11.22a ? current limit i ocl ? 2.4 4 a sink and source shutdown delay time t dsd 10 28 40 s sink and source 2.3 electrical characteristics (cont ? d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j <150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-3 g data sheet 12 2001-05-10 open circuit/underload detection detection current i ocd 15 30 45 ma ? delay time t doc 200 370 600 s ? output delay times; v s = 13.2 v; r load = 25 ? (device not in stand-by for t > 1 ms) source on t donh ? 820 s ? source off t doffh ? 420 s ? sink on t donl ? 720 s ? sink off t doffl ? 320 s ? dead time t dhl 13 ? s t donl ? t doffh dead time t dlh 15 ? s t donh ? t doffl output switching times; v s = 13.2 v; r load = 25 ? (device not in stand-by for t > 1 ms) source on t on h ? 520 s ? source off t off h ? 25 s ? sink on t on l ? 2.0 10 s ? sink off t off l ? 1.5 5 s ? clamp diodes forward voltage upper v fu ? 0.9 1.3 v i f = 0.5 a lower v fl ? 0.9 1.3 v i f = 0.5 a 2.3 electrical characteristics (cont ? d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-3 g data sheet 13 2001-05-10 inhibit input h-input voltage threshold v ih ? 0.52 0.7 v cc ? l-input voltage threshold v il 0.2 0.48 ? v cc ? hysteresis of input voltage v ihy 50 200 500 mv ? pull down current i i 5 25 100 a v i = 0.2 v cc input capacitance c i ? 10 15 pf 0 v < v cc < 5.25 v note: capacitances are guaranteed by design. spi-interface delay time from stand-by to data in/power on reset setup time t set ?? 100 s ? logic inputs di, clk and csn h-input voltage threshold v ih ? 0.52 0.7 v cc ? l-input voltage threshold v il 0.2 0.48 ? v cc ? hysteresis of input voltage v ihy 50 200 500 mv ? pull up current at pin csn i icsn ? 50 ? 25 ? 10 a v csn = 0.7 v cc pull down current at pin di i idi 10 25 50 a v di = 0.2 v cc pull down current at pin clk i iclk 10 25 50 a v clk = 0.2 v cc input capacitance at pin csn, di or clk c i ? 10 15 pf 0 v < v cc < 5.25 v note: capacitances are guaranteed by design. 2.3 electrical characteristics (cont ? d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j <150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-3 g data sheet 14 2001-05-10 logic output do h-output voltage level v doh v cc ? 1.0 v cc ? 0.7 ? v i doh =1 ma l-output voltage level v dol ? 0.2 0.4 v i dol = ? 1.6 ma tri-state leakage current i dolk ? 10 0 10 a v csn = v cc 0v < v do < v cc tri-state input capacitance c do ? 10 15 pf v csn = v cc 0v < v cc < 5.25 v note: capacitances are guaranteed by design. data input timing clock period t pclk 1000 ? ? ns ? clock high time t clkh 500 ? ? ns ? clock low time t clkl 500 ? ? ns ? clock low before csn low t bef 500 ? ? ns ? csn setup time t lead 500 ? ? ns ? clk setup time t lag 500 ? ? ns ? clock low after csn high t beh 500 ? ? ns ? di setup time t disu 250 ? ? ns ? di hold time t diho 250 ? ? ns ? input signal rise time at pin di, clk and csn t rin ? ? 200 ns ? input signal fall time at pin di, clk and csn t fin ? ? 200 ns ? 2.3 electrical characteristics (cont ? d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-3 g data sheet 15 2001-05-10 data output timing do rise time t rdo ? 50 100 ns c l = 100 pf do fall time t fdo ? 50 100 ns c l = 100 pf do enable time t endo ? ? 250 ns low impedance do disable time t disdo ? ? 250 ns high impedance do valid time t vado ? 100 250 ns v do < 0.2 v cc ; v do > 0.7 v cc ; c l = 100 pf thermal prewarning and shutdown thermal prewarning junction temperature t jpw 120 145 170 c ? temperature prewarning hysteresis ? t ? 30 ? k ? thermal shutdown junction temperature t jsd 150 175 200 c ? thermal switch-on junction temperature t jso 120 ? 170 c ? temperature shutdown hysteresis ? t ? 30 ? k ? ratio of sd to pw temperature t jsd / t jpw 1.05 1.20 ??? note: temperatures are guaranteed by design. the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. 2.3 electrical characteristics (cont ? d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j <150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-3 g data sheet 16 2001-05-10 3 timing diagrams figure 3 data transfer timing aet02177 0 12 3 4 5 6 7 8910 11 12 13 14 15 0 1 ++ csn clk di do hs1 e.g. old data actual data time new data actual status csn high to low & rising edge of clk: do is enabled. status information is transferred to output shift register csn low to high: data from shift-register is transferred to output power switches actual data previous status di: data will be accepted on the falling edge of clk-signal do: state will change on the rising edge of clk-signal time time time time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - -- 0 1 4 0 12 3 5 6 7 89 12 10 11 13 14 15 0 1
tle 6208-3 g data sheet 17 2001-05-10 figure 4 timing for temperature prewarning only figure 5 spi-input timing aet02620 csn clk di do time csn high to low & clk stays low: status information of data bit 0 (temperature prewarning) is transfered to do di: data is not accepted do: status information of data bit 0 (temperature prewarning) will stay as long as csn is low time time time 0 - aet02178 di valid don ? t care valid don ? t care don ? t care cc v 0.7 0.2 v cc bef t t lead clkh t t clkl beh t lag t t diho t disu clk csn cc v 0.2 0.7 v cc cc v 0.2 0.7 v cc
tle 6208-3 g data sheet 18 2001-05-10 figure 6 turn off/on time figure 7 do valid data delay time and valid time aet02179 csn don t 20% 70% t rin fin t off t doff t off state on state off state on state on t case 1 case 2 out out 50% 50% 70% 20% 20% 70% 50% aet02180 clk t rin fin t (low to high) rdo t do do (high to low) fdo t t vado 10 ns 50% cc v 0.7 0.2 v cc cc v 0.7 v cc 0.2 cc v 0.7 v cc 0.2 _ <
tle 6208-3 g data sheet 19 2001-05-10 figure 8 do enable and disable time aet02181 csn t fin rin t do do 10 ns t endo endo t disdo t t disdo v cc to pullup pulldown to gnd 10 k ? 50% 50% 50% 0.7 v cc cc v 0.2 _ < 10 k ?
tle 6208-3 g data sheet 20 2001-05-10 figure 9 application circuit bias inhibit charge pump detect fault- spi 16 bit logic and latch ov uv tsd >1 11 3 1,7,8,14 2 12 13 10 4 5 6 9 gnd out 2 out 1 out 3 do clk di csn v cc s v aeb02441 drv1 drv2 drv3 inh p gnd cc v r wd q reset watchdog d tle 4278g d01 1n4001 d02 z39 s c 10 f 47 nf c d 22 f c q v s = 12v m m
tle 6208-3 g data sheet 21 2001-05-10 4 package outlines sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm smd = surface mounted device p-dso-14-9 (plastic dual small outline package) gps09222

▲Up To Search▲

Price & Availability of TLE6208-3G

	To Download TLE6208-3G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .